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Hennessy, Patterson's Computer Organization And Design - The Hardware Software PDF

By Hennessy, Patterson

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8 cycles/instructions of that is due to multiplication instructions. 6% of the CPU time. 6. The clock rate will reduce by a factor of 5/6 . 6 times as good as the original. So the modification is detrimental and should not be made. 47 No solution provided. 48 Benchmarking suites are only useful as long as they provide a good indicator of performance on a typical workload of a certain type. This can be made untrue if the typical workload changes. Additionally, it is possible that, given enough time, ways to optimize for benchmarks in the hardware or compiler may be found, which would reduce the meaningfulness of the benchmark results.

1 * T If swap instructions are greater than 5% of the instruction mix, then a hardware implementation would be preferable. Address(trs) addi $rs,$rs,l Two cycles instead of one. This time the hardware implementation is more efficient if the load with increment instruction constitute more than 10% of the instruction mix. 28 Load instructions are on the critical path that includes the following functional units: instruction memory, register file read, ALU, data memory, and register file write. Increasing the delay of any of these units will increase the clock period of this datapath.

Once we recognize the instruction as 1 u i (in cycle 2), we will be ready to store the immediate field into the register file the next cycle. 26. 1. Instruction fetch step: Unchanged. 2. Instruction decode: Also unchanged, but the immediate field extraction and shifting will be done in this cycle as well. Solution* for Chapter B Exercises 3. Now the final form of the immediate value is ready to be loaded into the register file. The MemtoReg control signal has to be modified in order to allow its multiplexor to select the immediate upper field as the write data source.

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Computer Organization And Design - The Hardware Software Interface. Solutions by Hennessy, Patterson

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